DK-DEV-5SGXEA7N【PDF 85/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51005

2014.01.10

Stratix V PLLs

4-15

Figure 4-16: Example of clkena Signals

This figure shows a waveform example for a clock output enable. The clkena signal is synchronous to the

falling edge of the clock output.

Clock Select

Multiplexer Output

Use the clkena signals to

enable or disable the GCLK

clkena

and RCLK networks or the

FPLL_<#>_CLKOUT pins.

AND Gate Output

with R2 Bypassed

(ena Port Registered as

Falling Edge of Input Clock)

AND Gate Output

with R2 Not Bypassed

(ena Port Registered as Double

Register with Input Clock)

Stratix V devices have an additional metastability register that aids in asynchronous enable and disable of

the GCLK and RCLK networks. You can optionally bypass this register in the Quartus II software.

The PLL can remain locked, independent of the clkena signals, because the loop-related counters are not

affected. This feature is useful for applications that require a low-power or sleep mode. The clkena signal

can also disable clock outputs if the system is not tolerant of frequency overshoot during resynchronization.

Stratix V PLLs

PLLs provide robust clock management and synthesis for device clock management, external system clock

management, and high-speed I/O interfaces.

The Stratix V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs.

The output counters in Stratix V devices are dedicated to each fractional PLL that support integer or fractional

frequency synthesis.

Two adjacent PLLs share 18 C output counters. Any number of C counters can be assigned to each PLL, as

long as the total number used by the two PLLs is 18 or less.

The Stratix V devices offer up to 32 fractional PLLs in the larger densities. All Stratix V fractional PLLs have

the same core analog structure and features support.

Table 4-5: PLL Features in Stratix V Devices

Feature

Integer PLL

Clock Networks and PLLs in Stratix V Devices

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